1. Field of the Invention
The present invention generally relates to a flat panel display device and more particularly to dielectric layers within the flat panel display.
2. Description of the Related Art
Plasma display panels and liquid crystal displays are frequently used for flat panel displays. Liquid crystal displays (LCD) generally contain two glass substrates joined together with a layer of a liquid crystal material sandwiched therebetween. The glass substrates have conductive films coated thereon with at least one of the substrates being transparent such as an indium tin oxide (ITO) film. The substrates may be connected to a source of power to change the orientation of the liquid crystal material. Various areas of the liquid crystal cell can be accessed by proper patterning of the conductive films. More recently, thin film transistors (TFT) have been used to separately address areas of the liquid crystal cell at very fast rates. Such liquid crystal cells are useful for active matrix displays such as TV and computer monitors.
As the requirements for resolution of liquid crystal monitors increase, it has become desirable to address a large number of separate areas of the liquid crystal cell, called pixels. In a modern display panel, more than 1,000,000 pixels may be present. At least the same number of transistors are formed on the glass plates such that each pixel can be separately addressed and left in the switched state while other pixels are addressed. Generally, three transistors are formed on the glass plates per pixel.
One type of thin film transistor device used is the back channel etched thin film transistor (BCE TFT). A major CVD process step in conventional BCE TFT processing is the sequential deposition of three layers; an insulating dielectric layer of typically a gate silicon nitride, gate silicon oxide, or both, followed by an intrinsic (un-doped) amorphous silicon (i-a-Si) layer, and then a thin layer of phosphorus-doped amorphous silicon (N+-a-Si).
Plasma display panels generally include an upper substrate and a lower substrate. The upper substrate includes a dielectric layer deposited on scan electrodes and sustain electrodes. The lower substrate includes a dielectric layer formed on the surface of the lower substrate.
As device dimensions have diminished and device switching speeds have increased, circuit operation has become increasingly limited by capacitance delays due to the close proximity of conductor lines. Efforts to minimize the capacitance have been devoted to improving the quality of the dielectric materials forming the layers separating the conductor interconnection pattern. Silicon containing materials, such as silicon oxide and silicon nitride, have been used as dielectric materials for forming inter-metal dielectric (IMD) layers. The dielectric constants of these materials, whose values range from about 4 to about 8, result in undesirably high capacitance leading to increased signal coupling and cross-talk between adjacent conductor lines. Dielectric materials with lower dielectric constants suitable for forming dielectric layers have been developed such as, but not limited to, silsesquioxane spin-on-glass (SOG) dielectric materials, amorphous carbon dielectric materials, and organic polymer spin-on-polymer (SOP) dielectric materials, which exhibit dielectric constants in a range from about 2.5 to about 3.3. However, the low dielectric materials are porous and typically are used with liner layers having high dielectric constants that increase the overall dielectric constant of a multi-component dielectric layer.
The organic materials prepared by spin-coating technology generally present integration problems, such as poor adhesion, thermal instability and anisotropy of the dielectric constant. Therefore, there remains a need for dielectric layers having low dielectric constants for use as insulating layers in sub-micron flat panel displays.